What are the various revisions of PA-RISC? Updated: 01/23/03

Rev Bits Rel Models
1.0 32-bit '86 TS1, NS, NS1, CS1, NS2, PCx
1.1 32-bit '89 PA7000 (PCx-S), PA7100 (PCx-T), PA7150 (PCx-T+),
PA7100LC (PCx-L), PA7200 (PCx-T'), PA7300LC (PCx-L2)
2.0 64-bit '94 PA8000 (PCx-U), PA8200 (PCx-U+), PA8500 (PCx-W),
PA8600 (PCx-W+),PA8700 (PCx-W2), PA8800, PA8900

o The PA8700 is scheduled for release in the first half of 2001.
o The PA8800 is slated for release in the first half of 2002.
o The PA8900 is slated for release in the first half of 2003, and will
probably be the final processor in the PA-RISC family.

o HP-UX 10.10 is the last supported release for all PA-RISC 1.0 systems.
o HP-UX 10.20 is the first supported release for PA-RISC 2.0 systems.
o HP-UX 11.00 is the first release to utilize the 64-bit capacity of
PA-RISC 2.0.

PA-RISC architecture evolution
When the original PA-RISC 1.0 Architecture was designed in the early
eighties, its goal was to be a single architecture that efficiently spans
Hewlett-Packard's three computer lines: the HP3000 commercial
minicomputers, the HP9000 technical workstations and servers, and the
HP1000 realtime controllers. Before introduction, the program was
codenamed SPECTRUM. At introduction in 1986, it was known as HP's
Precision Architecture, HP-PA, or just PA. Subsequently, the
architecture was called PA-RISC, with the first version of the
architecture known as PA-RISC 1.0.

Since its introduction, the PA-RISC architecture has remained remarkably
stable. Only minor changes were made over the next decade, to facilitate
higher performance in floating-point and system processing. When PA-RISC
1.0 was designed, floating-point performance was not essential for the
majority of the HP computer systems targeted at that time. Hence, the
architecture defined floating-point support as optional coprocessor
instructions, without emphasizing high performance. In 1989, driven by
the performance needs of the HP9000 technical workstation line, PA-RISC
1.1 was introduced. This included additional floating-point capabilities,
such as more floating-point registers, doubling the amount of register
space for single-precision floating-point numbers, and introducing
combined operation floating-point instructions[3]. These floating-point
features enabled higher performance in technical computations, including
graphics, where single-precision floating-point numbers are extensively

In the system area, PA-RISC 1.1 architectural extensions were made to
speed up the processing of performance-sensitive abnormal events, such as
misses in the address translation cache (also called the TLB). Such
architectural changes are only visible to the operating system, and do
not affect any applications programs. Minor system changes have been
added to the three editions of the PA-RISC 1.1 architecture, known as
editions 1, 2 and 3, respectively, of the architecture manual.

PA-RISC 1.1 also added bi-endian support. Previously, PA-RISC 1.0 was a
consistently big endian machine, but in PA-RISC 1.1, support for little
endian was also provided by means of a mode bit.

The PA-RISC 2.0 architecture represents the first time that user-visible
changes have been made to the core integer architecture. In addition to
support for 64-bit integer data and 64-bit flat addresses, other
user-visible changes have also been added to enhance the performance of
new user workloads. For example, Multimedia Acceleration eXtensions (MAX)
have been added to speedup multimedia processing by software running on
the main processor, rather than on separate optional hardware. Some
additional floating-point and system-level changes have also been added.

(Excerpt from "64-bit and Multimedia Extensions in the PA-RISC 2.0
Architecture" by Ruby Lee <rblee@ee.princeton.edu> and Jerry Huck
<huck@cup.hp.com>, (c)Hewlett-Packard, 01/15/97)

For further information on PA-RISC processors, see the below URLs:

o <http://cpus.hp.com/technical_references/parisc.shtml>

For a description of considerations for 32-bit and 64-bit program
development, including cross-platform development, see:

o <http://devrsrc1.external.hp.com/STK/crossplatform.html>

You can expect programs compiled on a particular release of HP-UX to run
on that release, or on any later release, but NOT on an earlier release.
Hence, a program compiled on 11.00 can not be expected to run on 10.20.

The HP compilers' scheduling option, +DS xxx, does not affect the
compatibility of the generated object code. It affects only how the
optimizer schedules instructions that have long latencies, so it is
usually to your advantage to schedule the code for the fastest machine
currently shipping, even if you are generating code for an earlier

HP will gradually transition its servers from PA-RISC to the new
Itanium[TM] processor family (IPF), also known as IA-64, starting in mid
2001. The IA-64 architecture was co-developed by Intel and HP, and so it
inherits many features (and instructions) from PA-RISC. PA-RISC binaries
will run on IA-64 systems.

Intel's Itanium roadmap can be viewed at:

o <http://www.openvms.org/hp/intel_itanium_roadmap.jpg>

For more information on Itanium[TM], visit:

o <http://www.hp.com/products1/itanium/>

Information on transitioning to IA-64 is available as part of the HP-UX
11.x Software Transition Kit:

o <http://devrsrc1.external.hp.com/STK/>

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